ASIC/FPGA MICROELECTRONICS
DESIGN

ARQUIMEA provides analog, digital and mixed-signal microelectronics, including IP cores, ASIC, FPGA, ASSP and standard components. We deliver end-to-end solutions, from requirements definition, feasibility analysis and technology selection up to chip design, manufacturing and qualification as per the space standards.

We specialize in integrated circuits based on commercial technologies and hardened by design against the effects of cosmic and environmental radiation.

We are fabless. We provide the most suitable technology for each application: high voltage, high speed, low power… Our expertise goes from mature nodes up to deep submicron (22nm and below).

Main projects

 REDSAT ASIC set ELSA: Chip Set for reconfigurable active antenna control. Qualified for GEO telecommunications satellite. 1500+ flight units delivered since 2012 (customer: Airbus Defence & Space).

 COSMIC VISION reconfigurable mixed-signal ASICs (customer European Space Agency – ESA).

 Mixed-Signal ASIC for Avionics (OBC+PCDU) control in low-cost satellites (customer: IHP Microelectronics).

 SWIPE ASIC for Radiometry (EU FP7 Program).

 Design and integration of a RH ADC IP for a Scalable Sensor Data Processor ASIC (SSDP) (customer: Thales Alenia Space – ESA Project).

 QUANTUM – Fast Beam Hopping Enabled Digital ASIC for GEO telecommunications satellite (customer: Airbus Defence & Space).

 TMTC ASIC – Mixed-signal ASIC for telemetry and telecommand in PCDUs and ICUs (customer: Airbus Defence & Space).

 QUANTUM – Space FPGA’s implementation and verification (customer: Airbus Defence & Space).

SPAINSAT NG – Chip Set for reconfigurable active antenna control in GEO telecommunications satellite (customer: Airbus Defence & Space).

Rad-Hard LVDS Driver. LVDS Receiver. LVDS Transceiver. LVDS Repeater (customer: ESA – European Components Initiative)

SEPHY – 10/100Mbps Space Ethernet Physical Layer Transceiver (Customer: European Commission – H2020).

SECHIS – SERDES Chip for Space Applications (Customer: European Commission – Eurostars).

Verification of SEU-Mitigation Techniques in 3rd/4th Generation Flash FPGAs (Customer: European Commission – ESA).

Evaluation of 22nm Fully-depleted Silicon-On-Insulator technology for Space (Customer: European Commission – H2020).

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